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MODERN RECEIVERFRONT-ENDS
Systems, Circuits, and Integration
Publication Date: February 13, 2004 | ISBN-10: 0471225916 | ISBN-13: 978-0471225911 | Edition: 1
CONTENTS
Preface xi
Acknowledgments xiii
1 INTRODUCTION 1
1.1 Current State of the Art 3
2 RECEIVER SYSTEM DESIGN 7
2.1 Frequency Planning 7
2.1.1 Blockers 8
2.1.2 Spurs and Desensing 10
2.1.3 Transmitter Leakage 10
2.1.4 LO Leakage and Interference 11
2.1.5 Image 13
2.1.6 Half IF 13
2.2 Link Budget Analysis 14
2.2.1 Linearity 15
2.2.2 Noise 16
2.2.3 Signal-to-Noise Ratio 19
2.2.4 Receiver Gain 20
2.3 Propagation Effects 21
2.3.1 Path Loss 22
2.3.2 Multipath and Fading 23
2.3.3 Equalization 24
v
2.3.4 Diversity 24
2.3.5 Coding 24
2.4 Interface Planning 25
2.5 Conclusion 25
3 REVIEW OF RECEIVER ARCHITECTURES 27
3.1 Heterodyne Receivers 28
3.2 Image Reject Receivers 30
3.2.1 Hartley Architecture 31
3.2.2 Weaver Architecture 32
3.3 Zero IF Receivers 32
3.4 Low IF Receivers 34
3.5 Issues in Direct Conversion Receivers 34
3.5.1 Noise 38
3.5.2 LO Leakage and Radiation 38
3.5.3 Phase and Amplitude Imbalance 38
3.5.4 DC Offset 39
3.5.5 Intermodulations 41
3.6 Architecture Comparison and Trade-off 43
3.7 Conclusion 43
4 SILICON-BASED RECEIVER DESIGN 47
4.1 Receiver Architecture and Design 48
4.1.1 System Description and Calculations 48
4.1.2 Basics of OFDM 48
4.1.3 System Architectures 50
4.1.4 System Calculations 52
4.2 Circuit Design 54
4.2.1 SiGe BiCMOS Process Technology 54
4.2.2 LNA 55
4.2.3 Mixer 57
4.2.4 Frequency Divider 61
4.3 Receiver Design Steps 61
4.3.1 Design and Integration of Building Blocks 62
4.3.2 DC Conditions 62
4.3.3 Scattering Parameters 62
4.3.4 Small-Signal Performance 63
4.3.5 Transient Performance 64
4.3.6 Noise Performance 64
4.3.7 Linearity Performance 65
4.3.8 Parasitic Effects 68
4.3.9 Process Variation 68
4.3.10 50- and Non-50- Receivers 68
4.4 Layout Considerations 69
vi CONTENTS
4.5 Characterization of Receiver Front-Ends 70
4.5.1 DC Test 71
4.5.2 Functionality Test 71
4.5.3 S-Parameter Test 71
4.5.4 Conversion Gain Test 73
4.5.5 Linearity Test 74
4.5.6 Noise Figure Test 74
4.5.7 I/Q Imbalance 74
4.5.8 DC Offset 74
4.6 Measurement Results and Discussions 76
4.6.1 Close Examination of Noise Figure and I/Q Imbalance 79
4.6.2 Comments on I/Q Imbalance 79
4.7 Conclusion 80
5 SUBHARMONIC RECEIVER DESIGNS 83
5.1 Illustration of Subharmonic Techniques 84
5.2 Mixing Using Antisymmetric I–V Characteristics 85
5.3 Impact of Mismatch Effects 89
5.4 DC Offset Cancellation Mechanisms 92
5.4.1 Intrinsic DC Offset Cancellation 92
5.4.2 Extrinsic DC Offset Cancellation 93
5.5 Experimental Verification of DC Offset 94
5.6 Waveform Shaping Before Mixing 98
5.6.1 Theory and Analysis 101
5.6.2 Experimental Verification on GaAs MESFET APDP 102
5.6.3 Implementation in Silicon 106
5.7 Design Steps for APDP-Based Receivers 109
5.8 Architectural Illustration 111
5.9 Fully Monolithic Receiver Design Using Passive APDP Cores 112
5.9.1 Integrated Direct Conversion Receiver MMIC’s 112
5.9.2 Receiver Blocks 113
5.9.3 Additional Receiver Blocks 121
5.10 Reconfigurable Multiband Subharmonic Front-Ends 124
5.11 Conclusion 125
6 ACTIVE SUBHARMONIC RECEIVER DESIGNS 127
6.1 Stacking of Switching Cores 128
6.1.1 Description and Principles 128
6.1.2 Subharmonic Receiver Architecture 131
6.2 Parallel Transistor Stacks 132
6.2.1 Active Mixer 132
6.2.2 Receiver Architecture 134
6.2.3 Extension to Passive Mixers 137
6.3 Extension to Higher-Order LO Subharmonics 137
CONTENTS vii
6.4 Multiple Phase Signal Generation from Oscillators 139
6.5 Future Direction and Conclusion 140
7 DESIGN AND INTEGRATION OF PASSIVE COMPONENTS 143
7.1 System on Package (SoP) 144
7.1.1 Multilayer Bandpass Filter 146
7.1.2 Multilayer Balun Structure 148
7.1.3 Module-Integrable Antennaw 149
7.1.4 Fully Integrated SoP Module 149
7.2 On-Chip Inductors 152
7.2.1 Inductor Modeling 153
7.2.2 Inductor Parameters 157
7.2.3 Application in Circuits 158
7.3 Capacitors 159
7.4 Differentially Driven Inductors 163
7.5 Transformers 166
7.5.1 Electrical Parameters 166
7.5.2 Physical Construction 168
7.5.3 Electrical Models 168
7.5.4 Frequency Response of Transformers 172
7.5.5 Step-Up/Step-Down Transformers and 176
Circuit Applications
7.6 On-Chip Filters 177
7.6.1 Filters Using Bond Wires 179
7.6.2 Active Filters 179
7.7 On-Wafer Antennas 185
7.8 Wafer-Level Packaging 187
7.9 Conclusion 188
8 DESIGN FOR INTEGRATION 191
8.1 System Design Considerations 191
8.1.1 I/O Counts 191
8.1.2 Cross-Talk 192
8.1.3 Digital Circuitry Noise 193
8.2 IC Floor Plan 193
8.2.1 Signal Flow and Substrate Coupling 196
8.2.2 Grounding 196
8.2.3 Isolation 197
8.3 Packaging Considerations 198
8.3.1 Package Modeling 199
8.3.2 Bonding Limitation 200
8.4 Conclusion 200
9 FUTURE TRENDS 203
9.1 CMOS Cellphones 00
viii CONTENTS
9.2 Multiband, Multimode Wireless Solutions 204
9.3 60 GHz Subsystems in Silicon! 205
9.4 Interchip Communications 206
9.5 Ultrawideband Communication Technology 210
9.6 Diversity Techniques 211
9.7 Conclusion 213
Index 217
http://www.mediafire.com/download.php?m8c0aj6ua3d47sp
Systems, Circuits, and Integration
Publication Date: February 13, 2004 | ISBN-10: 0471225916 | ISBN-13: 978-0471225911 | Edition: 1
CONTENTS
Preface xi
Acknowledgments xiii
1 INTRODUCTION 1
1.1 Current State of the Art 3
2 RECEIVER SYSTEM DESIGN 7
2.1 Frequency Planning 7
2.1.1 Blockers 8
2.1.2 Spurs and Desensing 10
2.1.3 Transmitter Leakage 10
2.1.4 LO Leakage and Interference 11
2.1.5 Image 13
2.1.6 Half IF 13
2.2 Link Budget Analysis 14
2.2.1 Linearity 15
2.2.2 Noise 16
2.2.3 Signal-to-Noise Ratio 19
2.2.4 Receiver Gain 20
2.3 Propagation Effects 21
2.3.1 Path Loss 22
2.3.2 Multipath and Fading 23
2.3.3 Equalization 24
v
2.3.4 Diversity 24
2.3.5 Coding 24
2.4 Interface Planning 25
2.5 Conclusion 25
3 REVIEW OF RECEIVER ARCHITECTURES 27
3.1 Heterodyne Receivers 28
3.2 Image Reject Receivers 30
3.2.1 Hartley Architecture 31
3.2.2 Weaver Architecture 32
3.3 Zero IF Receivers 32
3.4 Low IF Receivers 34
3.5 Issues in Direct Conversion Receivers 34
3.5.1 Noise 38
3.5.2 LO Leakage and Radiation 38
3.5.3 Phase and Amplitude Imbalance 38
3.5.4 DC Offset 39
3.5.5 Intermodulations 41
3.6 Architecture Comparison and Trade-off 43
3.7 Conclusion 43
4 SILICON-BASED RECEIVER DESIGN 47
4.1 Receiver Architecture and Design 48
4.1.1 System Description and Calculations 48
4.1.2 Basics of OFDM 48
4.1.3 System Architectures 50
4.1.4 System Calculations 52
4.2 Circuit Design 54
4.2.1 SiGe BiCMOS Process Technology 54
4.2.2 LNA 55
4.2.3 Mixer 57
4.2.4 Frequency Divider 61
4.3 Receiver Design Steps 61
4.3.1 Design and Integration of Building Blocks 62
4.3.2 DC Conditions 62
4.3.3 Scattering Parameters 62
4.3.4 Small-Signal Performance 63
4.3.5 Transient Performance 64
4.3.6 Noise Performance 64
4.3.7 Linearity Performance 65
4.3.8 Parasitic Effects 68
4.3.9 Process Variation 68
4.3.10 50- and Non-50- Receivers 68
4.4 Layout Considerations 69
vi CONTENTS
4.5 Characterization of Receiver Front-Ends 70
4.5.1 DC Test 71
4.5.2 Functionality Test 71
4.5.3 S-Parameter Test 71
4.5.4 Conversion Gain Test 73
4.5.5 Linearity Test 74
4.5.6 Noise Figure Test 74
4.5.7 I/Q Imbalance 74
4.5.8 DC Offset 74
4.6 Measurement Results and Discussions 76
4.6.1 Close Examination of Noise Figure and I/Q Imbalance 79
4.6.2 Comments on I/Q Imbalance 79
4.7 Conclusion 80
5 SUBHARMONIC RECEIVER DESIGNS 83
5.1 Illustration of Subharmonic Techniques 84
5.2 Mixing Using Antisymmetric I–V Characteristics 85
5.3 Impact of Mismatch Effects 89
5.4 DC Offset Cancellation Mechanisms 92
5.4.1 Intrinsic DC Offset Cancellation 92
5.4.2 Extrinsic DC Offset Cancellation 93
5.5 Experimental Verification of DC Offset 94
5.6 Waveform Shaping Before Mixing 98
5.6.1 Theory and Analysis 101
5.6.2 Experimental Verification on GaAs MESFET APDP 102
5.6.3 Implementation in Silicon 106
5.7 Design Steps for APDP-Based Receivers 109
5.8 Architectural Illustration 111
5.9 Fully Monolithic Receiver Design Using Passive APDP Cores 112
5.9.1 Integrated Direct Conversion Receiver MMIC’s 112
5.9.2 Receiver Blocks 113
5.9.3 Additional Receiver Blocks 121
5.10 Reconfigurable Multiband Subharmonic Front-Ends 124
5.11 Conclusion 125
6 ACTIVE SUBHARMONIC RECEIVER DESIGNS 127
6.1 Stacking of Switching Cores 128
6.1.1 Description and Principles 128
6.1.2 Subharmonic Receiver Architecture 131
6.2 Parallel Transistor Stacks 132
6.2.1 Active Mixer 132
6.2.2 Receiver Architecture 134
6.2.3 Extension to Passive Mixers 137
6.3 Extension to Higher-Order LO Subharmonics 137
CONTENTS vii
6.4 Multiple Phase Signal Generation from Oscillators 139
6.5 Future Direction and Conclusion 140
7 DESIGN AND INTEGRATION OF PASSIVE COMPONENTS 143
7.1 System on Package (SoP) 144
7.1.1 Multilayer Bandpass Filter 146
7.1.2 Multilayer Balun Structure 148
7.1.3 Module-Integrable Antennaw 149
7.1.4 Fully Integrated SoP Module 149
7.2 On-Chip Inductors 152
7.2.1 Inductor Modeling 153
7.2.2 Inductor Parameters 157
7.2.3 Application in Circuits 158
7.3 Capacitors 159
7.4 Differentially Driven Inductors 163
7.5 Transformers 166
7.5.1 Electrical Parameters 166
7.5.2 Physical Construction 168
7.5.3 Electrical Models 168
7.5.4 Frequency Response of Transformers 172
7.5.5 Step-Up/Step-Down Transformers and 176
Circuit Applications
7.6 On-Chip Filters 177
7.6.1 Filters Using Bond Wires 179
7.6.2 Active Filters 179
7.7 On-Wafer Antennas 185
7.8 Wafer-Level Packaging 187
7.9 Conclusion 188
8 DESIGN FOR INTEGRATION 191
8.1 System Design Considerations 191
8.1.1 I/O Counts 191
8.1.2 Cross-Talk 192
8.1.3 Digital Circuitry Noise 193
8.2 IC Floor Plan 193
8.2.1 Signal Flow and Substrate Coupling 196
8.2.2 Grounding 196
8.2.3 Isolation 197
8.3 Packaging Considerations 198
8.3.1 Package Modeling 199
8.3.2 Bonding Limitation 200
8.4 Conclusion 200
9 FUTURE TRENDS 203
9.1 CMOS Cellphones 00
viii CONTENTS
9.2 Multiband, Multimode Wireless Solutions 204
9.3 60 GHz Subsystems in Silicon! 205
9.4 Interchip Communications 206
9.5 Ultrawideband Communication Technology 210
9.6 Diversity Techniques 211
9.7 Conclusion 213
Index 217
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